Phase interpolators are circuits that are used in many types of electronic systems, such as, for example, clock-data recovery systems. A phase interpolator receives as inputs a phase selection signal and two or more phase input signals having the same frequency as each other but offset in phase from each other. In response to these inputs, the phase interpolator produces a phase output signal having a phase specified by the phase selection signal. The phase interpolator produces the phase output signal by mixing two of the phase input signals in a ratio derived from the phase selection signal.
As illustrated in FIG. 1, a known phase interpolator 10 includes an adaptive bias generator 12, a triangle wave generator (TWG) 14, a fixed-bias phase mixer 16, phase control logic 18, and a logic level converter 20. Triangle wave generator 14 receives as inputs four phase input (clock) signals, each of which is offset from another by 90 degrees. For example, the four phase input signals can have phases relative to one another of zero degrees (PH0), 90 degrees (PH90), 180 degrees (PH180) and 270 degrees (PH270). Triangle wave generator 14 processes or conditions each of these four phase input signals by buffering the signal, and then using the buffered signal to control the charging and discharging of capacitor circuits (not separately shown). Triangle wave generator 14 includes one such capacitor circuit for each of the four phase input signals. Triangle wave generator 14 limits the current with which each of its four capacitor circuits is charged, such that the capacitor circuit charges for one-half clock cycle and discharges for one-half clock cycle.
As illustrated in FIG. 2, adaptive bias generator 12 in effect functions as a frequency-dependent current source that controls the bias current (I_BIAS_ADAPTIVE) with which triangle wave generator 14 charges each of its capacitors. The purpose of adaptive bias generator 12 is to compensate for (or “adapt” to) variations in mixer operating conditions, such as system clock frequency, supply voltage, etc. Adaptive bias generator 12 includes a comparator 22, a current source 24, two switches 26 and 28, a capacitor 30, and switch control logic 32. Switch control logic 32 controls switches 26 and 28 in response to the system clock. During the first half clock cycle of the system clock, switch control logic 32 closes switch 26 to charge capacitor 30 to a voltage Vsum while maintaining switch 28 open. During the second half clock cycle of the system clock, switch control logic 32 opens switch 26 and closes switch 28 to discharge capacitor 30 to ground. The combination of switches 26 and 28 and capacitor 30 is commonly referred to as a switched-capacitance resistor circuit 34. The feedback loop involving comparator 22 and current source 24 operates to ensure that the bias current (I_BIAS_ADAPTIVE) is sufficient to maintain Vsum equal to a reference voltage (V_REF) and thus to keep the bias current directly proportional to the frequency of the system clock. Thus, adaptive bias generator 12 directly adapts to or compensates for variations in system clock frequency and indirectly adapts to or compensates for voltage and temperature variations. Although not shown for purposes of clarity, current mirrors can be included to replicate the bias current for distribution to all four of the above-referenced capacitor circuits of triangle wave generator 14.
For example, in an instance in which the system clock signal has a frequency that is twice a frequency f, adaptive bias generator 12 generates a bias current that is twice the bias current that it generates when the system clock signal frequency is f. Using adaptive bias generator 12 to control the bias current with which triangle wave generator 14 charges each of its capacitors promotes a linear response to the system clock signal frequency. (Although not shown for purposes of clarity, it should be noted that the four phase input signals are generated from the system clock signal and therefore have the same frequency as the system clock signal.) Accordingly, triangle wave generator 14 generates four corresponding triangle-wave signals in response to the four square-wave phase input signals. The output of triangle wave generator 14 thus consists of four triangle-wave phase output signals having relative phases of zero degrees, 90 degrees, 180 degrees and 270 degrees.
Returning to FIG. 1, phase control logic 18 receives a phase selection signal as an input. The phase selection signal indicates a selected phase in a range greater than or equal to 0 degrees and less than 360 degrees. Phase control logic 18 determines which two of the four phase input signals the selected phase lies between and determines a ratio indicating the relative distances of the selected phase between those two phase input signals. For example, if the phase selection signal indicates a selected phase of 120 degrees, phase control logic 18 determines that the selected phase lies between the 90-degree phase input signal (PH90) and the 180-degree phase input signal (PH180) and determines that the selected phase of 120 degrees lies one-third of the distance (i.e., 90 degrees) from the 90-degree phase input signal to the 180-degree phase input signal, and correspondingly, two-thirds of the distance from the 180-degree phase input signal to the 90-degree phase input signal.
As illustrated in FIG. 3, fixed-bias phase mixer 16 includes a first buffer 36, a second buffer 38, a third buffer 40, and a fourth buffer 42. The input of first buffer 36 receives the 0-degree phase input signal, and the output of first buffer 36 is connected to a common node that serves as the output of fixed-bias phase mixer 16 (PH_OUT). The input of second buffer 38 receives the 90-degree phase input signal, and the output of second buffer 38 is connected to this common node. The input of third buffer 40 receives the 180-degree phase input signal, and the output of third buffer 40 is connected to the common node. The input of fourth buffer 42 receives the 270-degree phase input signal, and the output of fourth buffer 42 is connected to the common node.
First buffer 36 is driven by a bias current provided by a variable current source 44 and a variable current sink 46 that operate in tandem. That is, the source current (IP0) provided by variable current source 44 is equal to the current (IN0) sunk by variable current sink 46. First buffer 36 outputs a current that represents a proportion of the 0-degree phase input signal determined by this bias current (IP0 and IN0). First buffer 36, variable current source 44 and variable current sink 46 collectively define a first buffer circuit 48.
Likewise, second buffer 38 is driven by a bias current provided by a variable current source 50 and a variable current sink 52 that operate in tandem. That is, the source current (IP90) provided by variable current source 50 is equal to the current (IN90) sunk by variable current sink 52. Second buffer 38 outputs a current that represents a proportion of the 90-degree phase input signal determined by this bias current (IP90 and IN90). Second buffer 38, variable current source 50 and variable current sink 52 collectively define a second buffer circuit 54.
Similarly, third buffer 40 is driven by a bias current provided by a variable current source 56 and a variable current sink 58 that operate in tandem. That is, the source current (IP180) provided by variable current source 56 is equal to the current (IN180) sunk by variable current sink 58. Third buffer 40 outputs a current that represents a proportion of the 180-degree phase input signal determined by this bias current (IP180 and IN180). Third buffer 40, variable current source 56 and variable current sink 58 collectively define a third buffer circuit 60.
In the same manner, fourth buffer 42 is driven by a bias current provided by a variable current source 62 and a variable current sink 64 that operate in tandem. That is, the source current (IP270) provided by variable current source 62 is equal to the current (IN270) sunk by variable current sink 64. Fourth buffer 42 outputs a current that represents a proportion of the 270-degree phase input signal determined by this bias current (IP270 and IN270). Fourth buffer 42, variable current source 62 and variable current sink 64 collectively define a fourth buffer circuit 66.
Fixed-bias phase mixer 16 generates an output phase signal (PH_OUT) in accordance with the following equations:IPA=(1−X)*I_BIAS_FIXED,INA=(1−X)*I_BIAS_FIXED,IPB=X*I_BIAS_FIXED, andINB=X*I_BIAS_FIXED,where IPA and INA represent a first bias current (i.e., a selected one of the following pairs: IP0 and IN0; IP90 and IN90; IP180 and IN180; and IP270 and IN270), where IPB and INB represent a second bias current (i.e., a selected one of the following pairs: IP0 and IN0; IP90 and IN90; IP180 and IN180; and IP270 and IN270), where the selected phase is determined by phase control logic 18 to lie between a phase A and a phase B, where phase A corresponds to the phase input signal that is input to the one of buffers 36-42 driven by IPA and INA (which can be referred to for convenience as “the phase A buffer”), and phase B corresponds to the phase input signal that is input to the one of buffers 36-42 driven by IPB and INB (which can be referred to for convenience as “the phase B buffer”), where X represents the percentage distance between phase A and phase B, and where I_BIAS_FIXED is the sum of the bias current that drives the phase A buffer and the bias current that drives phase B buffer. Note that I_BIAS_FIXED remains fixed, i.e., it does not change in response to any other signal.
In response to the phase selection signal, phase control logic 18 determines phase A and phase B and accordingly determines IPA, INA, IPB and INB. That is, phase control logic 18 sets IPA, INA, IPB and INB by causing the above-described variable current source and sink corresponding to the phase A buffer to be set or adjusted to values of IPA and INA, and causing the above-described variable current sinks corresponding to the phase B buffer to be set or adjusted to values of IPB and INB, respectively. Phase control logic 18 also causes the variable current sources and sinks that do not correspond to the phase A or phase B buffers to be set to a value of zero. With regard to the example described above, in which the phase selection signal indicates a selected phase of 120 degrees and thus in which the selected phase lies between the 90-degree phase input signal (phase A) and the 180-degree phase input signal (phase B), where I_BIAS_FIXED is, for example, 2 mA:IP0=IN0=0,IP90=IN90=(1−0.33)*2=1.33 mA,IP180=IN180=0.33*2=0.67 mA, andIP270=IN270=0.
As illustrated in FIG. 4, each of buffer circuits 48, 54, 60 and 66 includes a number (n) of transistor groups, where a digital control word (C0x . . . Cnx) and its complement (NC0x . . . NCnx) received from phase control logic 18 each have n+1 bits. The “x” in the signal name (e.g., Cn“x”) identifies one of the four buffer circuits 48, 54, 60 and 66. The transistors can include P-channel and N-channel metal-oxide semiconductor field-effect transistors, commonly abbreviated as “PFET”s and “NFET”s, respectively. The n+1 transistor groups are identical to each other, and each is controlled by a corresponding bit of the control word. A first exemplary transistor group includes a first PFET 68, a second PFET 70, a first NFET 72, and a second NFET 74; corresponding transistors of a second exemplary transistor group, which is identical to the first exemplary transistor group, are labeled 68′, 70′, 72′ and 74′; corresponding transistors of a third exemplary transistor group, which is identical to the first and second exemplary transistor groups, are labeled 68″, 70″, 72″ and 74″; etc., through the nth transistor group, the corresponding transistors of which are labeled 68′″, 70′″, 72′″ and 74′″. Note that PFETs 68, 68′, 68″, 68′″, etc., collectively define an exemplary one of the variable current sources 44, 50, 56 and 62 described above with regard to FIG. 3. Similarly, note that NFETs 74, 74′, 74″, 74′″, etc., collectively define an exemplary one of the variable current sinks 46, 52, 58 and 64 described above with regard to FIG. 3. By adjusting the control word, phase control logic 18 can adjust the bias with which each of buffers 36-42 is driven to correspond to the control word. When buffers 36-42 are driven with bias currents corresponding to the control word, fixed-bias phase mixer 16 produces a triangle wave-format output phase signal (PH_OUT) having a phase corresponding to the phase selection signal. Logic level converter 20 (FIG. 1) converts the triangle wave-format output phase signal (PH_OUT) into a signal having a squarewave format, such as, for example, CMOS logic voltage levels.